Project Difficulty
Intermediate
Audience
Electronic Engineering
Description
This project aims to develop a reference design of AMBA (Advanced Microcontroller Bus Architecture) infrastructure. You are free to choose which AMBA protocol and version of the interconnect standard to implement with more simple specifications e.g., APB, being easier to create than coherent protocols such as AMBA CHI.
The main deliverables include the Verilog design of the AMBA infrastructure, a Verilog test bench for testing the design, an RTL (Register Transfer Level) simulation flow to verify the functionality, and an FPGA prototyping platform to demonstrate the design in a real-world environment. The project will provide a comprehensive understanding of AMBA protocols and their implementation, making it an excellent learning opportunity for students interested in digital design and hardware description languages.
Estimated Project Duration
The project is estimated to take 12 to 16 weeks to complete, involving a team of 3-4 participants. There is no hard deadline, but timely completion is encouraged to maximize learning outcomes.
Hardware / Software Requirements
- Languages: Verilog, SystemVerilog
- Tooling: ModelSim, Quartus, Vivado
- Hardware: FPGA development board (e.g., Xilinx or Altera), simulation tools
Resources
Previous Submissions
Similar projects: - https://github.com/kumarraj5364/AMBA-APB-PROTOCOL
Benefits / Prizes
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Standout projects could be internally referred for relevant positions at Arm!
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If your submission is approved, you will receive a recognised badge that you can list on your CV and shared on LinkedIn. A great way to stand out from the crowd!
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It’s a great way to demonstrate your initiative and commitment to your field.
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It offers the opportunity to learn valuable skills that are highly relevant to a successful career at Arm!
